1. Field of the Invention
The present invention relates in general to the design and use of a comparator and latch circuit. In one aspect, the present invention relates to a data sample circuit and methods for operating same.
2. Description of the Related Art
In high data-rate applications such as multimedia applications, there is increasing demand for high speed serial links which provide high speed signal conditioning and data capture capabilities, especially as the physical data rates continue to increase from one generation to the next. Sampler circuits are typically included in signal-conditioning systems (e.g., analog-to-digital converters), and function to successively capture or quantize a fast-moving input signal (e.g., the output of an analog signal processor) to provide samples that facilitate further processing in an associated signal-conditioning system (e.g., the digital signal processor). Conventional sampler circuits are implemented with current-mode logic (CML) latches, such as the CML latch 100 shown in FIG. 1, which samples the input signal, Vin and Vinx, in two phases referred to as the transparent phase and latch phase. In the transparent phase, the input signal (Vin and Vinx) is amplified with the CML amplifier pair (M1/R1 and M2/R2) when the clock signal clkx is high to turn on the input CML pair (M1 and M2), thereby allowing the output signals (out and outx) to follow the input signals (Vin and Vinx). In the latch phase, the input amplifier (M1, M2) is turned off and the cross-coupled latch pair (M3, M4) is turned on to amplify and latch the input voltage signal when the clock signal clk is high. The final voltage of the transparent phase or the initial voltage of the latch phase is thus latched by the cross-coupled nMOS pair M3, M4. The cross-coupled pair M3, M4 usually has a sufficient gain to ensure the input is latched promptly, and also has an output swing (negative or positive) at the end of the latch phase needed to overcome the output signal. This results in a strong hysteresis because, in the next transparent phase, the CML latch 100 needs to overcome such a high initial voltage and sense the input signal, which may be much smaller than the initial voltage.
To illustrate the performance of the latch 100, reference is now made to FIG. 2 which depicts timing diagram 200 for a conventional CML latch in which a test input signal Vin 203 is sampled at the rising edge of clock clk 204 using a load phase 201 and latch phase 202. In the load phase 201, the input amplifier transistors (M1, M2) sample the input signal 203, causing the output signal Vout 205 to follow the input signal Vin 203. In the latch phase 202, the cross-coupled latch pair (M3, M4) holds the output signal Vout 205 at the value sampled at the rising edge of clock clk 204. Because the CML latch in the load phase 201 has a time constant that is determined by the load resistance and capacitance at the latch output, the edge transition rate 206 of the output signal 205 can be quite slow, depending on the output load resistance and capacitance. This delayed transition rate 206 can reduce the data sampling eye, thereby impairing reliability and performance. When the input signal Vin 203 is near its zero-crossing point, a blind period is created where the sampler cannot reliably distinguish the polarity of its input signal because of the metastability and hysteresis of the sampler. As a result, the blind period reduces the sampling window, in which the sampler can properly operate, so that it is narrower than the actual eye width because of the non-ideal behavior of the sampler. Such degradation becomes more significant in high-speed receiver applications because of the reduced eye width.